• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    Methods and apparatus for pulse width modulation (PWM) signals 30, 130 are provided. The input is one of the digital signals, which are modulation signals 24 and 124. In the form shown, the modulated input signal is a PDM signal or a PCM signal. In one embodiment of the present invention, the PCM-PWM converters 16 and 116 include a duty ratio correction circuit 48. The method used may include a cycle of values obtained after prediction, interpolation, and correction. The digital-to-analog conversion system 10 uses a PDM-PWM converter 20 operating in the fully digital domain and does not include analog circuitry.
    公开号:KR20040071289A
    申请号:KR10-2004-7010503
    申请日:2002-12-13
    公开日:2004-08-11
    发明作者:로크너윌리엄제이.；미드야팔랍；워푸잔에이.；린더크네츠윌리엄제이.
    申请人:모토로라 인코포레이티드；
    IPC主号:
    专利说明:

    Method and apparatus for generating a pulse width modulated signal
    [2] Pulse width modulation (PWM) is a suitable method for generating power signals with high efficiency. In particular, many high efficiency digital audio switching power amplifiers are based on PWM signaling. Digital audio inputs to these amplifiers are typically pulse code modulated (PCM). Direct conversion from PCM to PWM to generate uniformly sampled PWM (UPWM) signals is a nonlinear operation that generates a large amount of harmonic distortion. In contrast, natural sampled PWM (NPWM) does not include harmonic distortion. Natural sampled PWM signals are easily generated in the analog domain by comparing the analog input signal with a sawtooth or triangle ramp signal. NPWM pulse edges are determined by the natural intersections between the input analog signal and the ramp signal. However, calculating natural intersection points for NPWM in the digital domain based on PCM input data can be computationally expensive.
    [3] Super Audio Compact Discs (SACD) are a new digital audio data format. Audio is digitized and stored in pulse density modulation (PDM) format. It consists of an oversampled (64 * Fs, where Fs is the initial sampling rate) 1-bit PDM data stream. It is desirable to convert the SACD bit stream (or any PDM bit stream) into a pulse width modulated (PWM) signal that can be used to drive a highly efficient switching digital audio amplifier. The SACD PDM bit stream can be used directly as a switching signal, but this approach does not easily allow implementation of any desired signal processing (ie, volume control, equalization, etc.).
    [4] Pulse density modulated signals (such as SACD) are typically shaped noise to repel quantization noise outside the associated frequency band. This generates a frequency spectrum that contains a large amount of out-of-band noise.
    [5] High performance switching digital audio amplifiers for SACD inputs are commercially available. However, to accommodate volume control, SACD PDM signals cannot be amplified directly. Instead, the PDM input signal should be treated as an analog signal that can be attenuated as required for volume control. This signal is then fed to a seventh order 1-bit sigma delta ADC modulator that generates a new PDM signal for amplification in the switching amplifier. The big drawback of this system is that the signal does not stay in the digital domain. The digital input signal is converted to analog to allow signal processing in the analog domain and then to digital (PDM) to drive the switching amplifier. All the advantages of maintaining a digital signal lineup are lost. In addition, the use of a PDM signal to drive a switching amplifier has some disadvantages compared to using a PWM signal. For example, PWM has a lower average switching frequency, which results in higher efficiency when compared to PDM. Moreover, the non-return-to-zero (NRZ) characteristic of the PDM signal may result in increased distortion when compared to the zero return PWM signal. Following the digital domain (volume control, equalization, etc.), processing of high speed 1-bit PDM signals in a digital sigma delta modulator may be considered. However, processing at such high bit rates can be very expensive.
    [6] Many common approaches to SACD modulation and amplification consist of decimating a high sample rate PDM to a low sample rate PCM, performing signal processing, performing digital-to-analog conversion, and amplifying in the analog domain. The major drawback of this approach is that all the advantages of high efficiency digital switching amplification are lost.
    [1] The present invention generally relates to pulse width modulation, and more particularly to converting a pulse density modulated data stream or a pulse code modulated data stream into a pulse width modulated signal.
    [9] 1 illustrates one embodiment of a digital-to-analog conversion system in accordance with the present invention.
    [10] 2 illustrates another embodiment of a digital-to-analog conversion system according to the present invention.
    [11] 3 shows an embodiment of a PCM-PWM converter according to the present invention.
    [12] 4 illustrates a number of signals used in the natural sampling circuit according to the present invention.
    [13] 5 shows one embodiment of a timing diagram for bidirectional PWM signals.
    [14] FIG. 6 illustrates in flowchart form the functions performed by the natural sampling circuit in accordance with one embodiment of the present invention. FIG.
    [15] 7 is a block diagram illustrating a general purpose computer used to implement one embodiment of the present invention.
    [7] Accordingly, there is a need for a computationally efficient method for fully converting both PDM and PCM encoded input signals to PWM switching waveforms in the digital domain to advantageously drive a switching digital power amplifier. This method must withstand out-of-band noise as commonly found in PDM signals.
    [8] The invention is illustrated by way of example and not by way of limitation, with reference to the accompanying drawings in which like reference numerals indicate like elements.
    [16] Those skilled in the art will understand that the elements of the figures are shown for simplicity and clarity and are not necessarily to scale. For example, the dimensions of some of the elements of the figures may be exaggerated relative to other elements to assist in improving the understanding of embodiments of the present invention.
    [17] 1 illustrates one embodiment of a digital-to-analog conversion system 10. In one embodiment of the present invention, the digital-to-analog conversion system 10 receives a pulse density modulation (PDM) signal 24 as input to the PDM-PWM converter 20. The PDM-PWM converter 20 then provides a pulse width modulated (PWM) signal 30 to the low pass filter 18. Low pass filter 18 provides an analog signal as an output to rod 22 (not shown). In one embodiment, the rod 22 may be an audio speaker. Other embodiments of the present invention may use other types of rods. In one embodiment of the invention, the PDM-PWM converter 20 includes a decimation filter 12, a digital signal conditioning circuit 14, and a PCM-PWM converter 16. In one embodiment, decimation filter 12 receives PDM signal 24 as input and provides pulse code modulation (PCM) signal 26 as output. PDM signal 24 has 1-bit resolution at high sample rates. The decimation filter 12 reduces the sample rate and increases the bit resolution that generates the pulse code modulation (PCM) signal 26. The digital signal conditioning circuit 14 receives the PCM signal 26 as an input and provides the adjusted PCM signal 28 as an output. The PCM-PWM converter 16 receives the adjusted PCM signal 28 as an input and provides the PWM signal 30 as an output to the low pass filter 18. Note that alternative embodiments of the present invention may optionally include an amplifier as part of the digital-to-analog conversion system 10. For example, an amplifier (not shown) may optionally be included between the transducer 16 and the low pass filter 18. Alternatively, an optional amplifier (not shown) may instead be included between the low pass filter 18 and the rod 22. Note that alternative embodiments of the present invention may combine the functions of the decimation filter 12 and the digital signal conditioning circuit 14 in any manner. Importantly, the function of the circuits 12 and 14 is to receive the PDM signal 24 as input and to provide the adjusted PCM signal as an output. The digital signal conditioning performed by the digital signal conditioning circuit 14 may be quite variable. For example, some embodiments of the present invention may use digital signal conditioning circuit 14 to provide volume control, graphic equalization, and any other desired digital effects or processing. Alternatively, digital signal adjustment may be performed before the decimation filter function.
    [18] 2 illustrates one embodiment of a digital-to-analog conversion system 110. In one embodiment of the present invention, digital-to-analog conversion system 110 receives pulse code modulation (PCM) signal 124 as input to PCM-PWM converter 120. The PCM-PWM converter 120 then provides a pulse width modulated (PWM) signal 130 to the low pass filter 118. Low pass filter 118 provides an analog signal as output to rod 122 (not shown). In one embodiment, rod 122 may be an audio speaker. Other embodiments of the present invention may use other types of rods. In one embodiment of the invention, the PCM-PWM converter 120 includes an oversampling circuit 112, a digital signal conditioning circuit 114, and a PCM-PWM converter 116. In one embodiment, oversampling circuit 112 receives PCM signal 124 as an input and provides an oversampled pulse code modulation (PCM) signal 126 as an output. The digital signal conditioning circuit 114 receives the oversampled pulse code modulation (PCM) signal 126 as an input and provides the adjusted PCM signal 128 as an output. PCM-PWM converter 116 receives the adjusted PCM signal 128 as input and provides a PWM signal 130 as output to the low pass filter 118. Note that alternative embodiments of the present invention may optionally include an amplifier as part of the digital-to-analog conversion system 110. For example, an amplifier (not shown) may optionally be included between the converter 116 and the low pass filter 118. Alternatively, an optional amplifier (not shown) may instead be included between the low pass filter 118 and the rod 122. Note that alternative embodiments of the present invention may combine the functions of the oversampling circuit 112 and the digital signal conditioning circuit 114 in any manner. Importantly, the function of the circuits 112 and 114 is to receive the PCM signal 124 as an input and provide the adjusted PCM signal as an output. The digital signal conditioning performed by the digital signal conditioning circuit 114 may be quite variable. For example, some embodiments of the present invention may use digital signal conditioning circuit 114 to provide volume control, graphic equalization, and any other desired digital effects or processing. Alternatively, digital signal adjustment may be performed before oversampling circuit function.
    [19] 3 shows one embodiment of the PCM-PWM converter 16 shown in FIG. 1 and the PCM-PWM converter 116 shown in FIG. 2. Although the PCM-PWM converters 16 and 116 are both shown in FIG. 3, alternative embodiments of the digital-to-analog conversion system 10 shown in FIG. 1 and the digital-to-analog conversion system 110 shown in FIG. Note that different embodiments of the PCM-PWM converter 16, 116 may be used. In Figure 3, note that the optional circuit and connections are shown in dashed lines. In one embodiment, the PCM-PWM converter 16, 116 includes a natural sampling circuit 40 and a PWM quantizer and a noise shaper 42. In one embodiment, the natural sampling circuit 40 receives the adjusted PCM signals (U) 28, 128 as input and provides a natural sample point output (X) 57 as an output. The PWM quantizer and noise shaper 42 receive the natural sample point output (X) 57 as input and provide PWM signals 30 and 130 as output. In one embodiment of the invention, the natural sampling circuit 40 includes a duty ratio predictor 44, a signal value interpolator 46, and a duty ratio correction circuit 48. In one embodiment of the invention, the duty ratio predictor 44 receives the adjusted PCM signals (U) 28, 128 as input signals and provides a time point guess (G) 50 as output. Signal value interpolator 46 receives time point guess (G) 50 as an input signal and provides an interpolated signal value (V) 52 as an output. Duty ratio correction circuit 48 receives the interpolated signal value (V) 52 as an input and provides a natural sample point output (X) 57 as an output. In one embodiment of the invention, the natural sample point output (X) 57 is provided as feedback to the duty ratio predictor 44 as the previous natural sample point output (X) 58. Further, in some embodiments of the present invention, the natural sample point output (X) 57 is fed back as an updated time point guess (G) 56 to the signal value interpolator 46. Further, in some embodiments of the present invention, the interpolated signal value (V) 52 is fed back as an updated time point guess (G) 59 input. Note that the feedback paths 56, 58, 59 are optional and may or may not be included in various embodiments of the present invention. Note also that the duty ratio predictor 44 is optional. Some embodiments of the present invention may directly provide the adjusted PCM signals (U) 28, 128 to the signal value interpolator 46. Note that the time point guess (G) 50 signal is also provided as an input to the duty ratio correction circuit 48. The adjusted PCM signals (U) 28, 128 are also provided as inputs to the signal value interpolator 46 and the duty ratio correction circuit 48. Note that if the duty ratio predictor 44 is not used, the time point guess (G) signal 50 is just the same as the adjusted PCM signal (U) 28, 128. Inputs to the PWM quantizer and noise shaper 42 are natural sample point outputs (X) 57 which are high resolution PWM signals. Thus, the PWM quantizer and noise shaper 42 quantize this high resolution PWM signal to produce lower resolution quantized PWM signals 30 and 130. In one embodiment, the noise shaping function of the circuit 42 shapes quantization noise outside the pass band.
    [20] With continued reference to FIG. 3, in one embodiment of the invention, the addition of the duty ratio correction circuit 48 greatly improves the accuracy of the natural sample point output (X) signal 57 produced by the transducers 16, 116. You can also increase it. Indeed, the addition of duty ratio correction circuit 48 to converters 16 and 116 allows duty ratio predictor 44 to be completely excluded for some applications. However, alternative embodiments of the present invention may use a combination of duty ratio correction circuit 48 and duty ratio predictor circuit 44. The addition of duty ratio correction circuit 48 may reduce the amount of memory and the number of calculations required by converters 16 and 116. The addition of the duty ratio correction circuit 48 also greatly improves the distortion performance of the natural sample point output (X) signal 57 and hence the distortion performance of the PWM signals 30, 130. In addition, the duty ratio correction circuit 48 produces a natural sample point output (X) signal 57 that is less sensitive to out-of-band noise. This is particularly important because the PDM signal 24 (see FIG. 1) generally has a significant amount of out-of-band noise.
    [21] 4 shows a time domain representation of several signals generated and / or used in the natural sampling circuit 40 (see FIG. 3) in which the unidirectional PWM signal is generated by using the sawtooth ramp signal 81. Alternative embodiments of the present invention may use lamps in addition to toothed. For example, FIG. 5 shows one embodiment of a timing diagram for a bidirectional PWM signal having a symmetrical triangular ramp signal 90. The left half of the ramp signal 90 is when the lamp is rising, and the right half of the ramp signal 90 is when the lamp is falling. Individual samples of the adjusted PCM signal (U) 28, 128 are selected to align with the centers of the ramp signal 81 or the ramp signal 90. Theoretical analog signal 80 and theoretical analog signal 91 represent an ideal analog signal corresponding to samples of the adjusted PCM signal (U) 28, 128. Exemplary bidirectional PWM signals 30 and 130 are shown in FIG. 5. The adjusted PCM signal (U) 28, 128 is selected to have even indices for the left half, and the odd indices are aligned with the right half of the PWM signal 30, 130.
    [22] 3 and 4, the time point guess (G) signal 50 calculates the value of the interpolated signal value (V) 52 using the adjusted PCM (U) signals 28, 128. Used. The interpolated signal value (V) 52 is not equal to the time point guess G 50 unless all errors are eliminated. The difference V-G is multiplied by the estimated signal slope S of the theoretical analog signal 80 to calculate the correction C 82. The natural sample point output (X) signal 57 is a corrected signal. Note that in one embodiment of the present invention, ramp signal 81 is selected to rise linearly between zero and one.
    [23] FIG. 6 illustrates, in flow chart form, the function performed by one embodiment of the natural sampling circuit 40 of FIG. 3. In one embodiment, flow 199 commences at the starting ellipse 200 and proceeds to step 203 where an estimation time G is provided. Step 203 provides a guess time G based on the adjusted PCM samples and / or the already calculated natural sample point output X. Flow 199 then proceeds to step 204 where the interpolated signal value V in the time point guess G is digitally calculated based on the adjusted PCM signal U. Next, flow 199 continues to crystal diamond 202 where a determination is made as to whether it is necessary to repeat step 204 using the interpolated signal value V as the next time point guess G. Crystal diamond 202 may be used to repeat step 204 N times, where N is an integer greater than or equal to zero. Thus, if N is zero, step 204 is executed only once and no cyclic looping occurs. Note that step 205 only indicates that step 204 will use the interpolated signal value (V) as the next time point guess (G). After repeating step 204 N times, flow 199 generates a correction (C) based on the most recent interpolated signal value (V) and the most recent time point estimate (G) and estimated signal slope (S). Continue to 206. From step 206, flow 199 continues at step 207 where the correction C is combined with the most recent interpolation signal value V to produce a natural sample point output X. From step 207, flow 199 continues at step 208 where the entire flow of 199 is repeated for each sample of the adjusted PCM signal U. From step 208, flow 199 continues at ellipse 201 where flow 199 ends. In alternative embodiments of the present invention, steps 206 and 207 may be moved before crystal diamond 202, so steps 206 and 207 are repeated as part of an iterative circulating loop. Note that in some embodiments of the present invention, the number used for N in crystalline diamond 202 may be a function of one of the values used in flow 199. For example, the value N at crystal diamond 202 may be a function of the correction value C. Note that alternative embodiments of the present invention may use any suitable method to provide a time point guess (G) as required in step 203. One example of a method for providing a time point guess (G) is described in US Patent Application No. 09 / 478,024 to Pallab Midya, filed Jan. 5, 2000.
    [24] It can be seen that the flow described in FIG. 6 performed by the transducers 16 and 116 in the order of interpolation produces a natural sample point output X that is nearly optimal when compared to the ideal natural sample in that order.
    [25] A mathematical description of one embodiment of the present invention will be provided using the following variables:
    [26] Sample index n
    [27] Adjusted PCM Signal U (n) (28, 128)
    [28] Time Point Guess G (n) (50)
    [29] Interpolated Signal Value V (n) (52)
    [30] Correction signal C (n) (82)
    [31] Natural Sample Point Output X (n) (57)
    [32] Guessing Time Points for Natural Sampling in the First Iteration: G 1 (n)
    [33] Interpolated signal value obtained by interpolation at sample point of first iteration: V 1 (n)
    [34] Correction of signal value in first iteration: C 1 (n)
    [35] Natural sample point output at first iteration: X 1 (n)
    [36] Guessing Time Points for Natural Sampling at the Second Iteration: G 2 (n)
    [37] Interpolated signal value obtained by interpolation at sample point of second iteration: V 2 (n)
    [38] Correction of signal value in second iteration: C 2 (n)
    [39] Natural sample point output at second iteration: X 2 (n)
    [40] The first step is to determine an initial time point guess (G) 50. In the most general form, it is derived from a combination of previous, present and future samples of the adjusted PCM signal (U) 28, 128 as well as past-computed samples of the natural sample point output (X) 57. Example cases are as follows.
    [41] (One)
    [42] or
    [43] (2)
    [44] or
    [45] (3)
    [46] The interpolated signal values (V) 52 of the theoretical analog signals 80 and 91 at the guess time points are calculated based on the interpolation equation. In some embodiments of the invention, it is observed that better accuracy may be achieved when uniform samples of the adjusted PCM signal (U) 28, 128 are aligned with the center of the ramps 81, 90. By using this approach for bidirectional PWM (see Figure 5), the interpolated signal value (V) 52 for the left PWM case can be calculated as follows.
    [47] (4)
    [48] Similar equations are maintained for the right hand side.
    [49] (5)
    [50] All of these equations are based on a three-point second order Lagrange interpolation formula. Other types of Lagrangian interpolation as well as other types of interpolation may be substituted based on accuracy and computational constraints.
    [51] The next step is the calibration step. The correction step is based on the idea that the value of the interpolated signal value (V) 52 is very close to the ramp when the time point guess G is close to the ideal natural sample time point. Therefore, the signal value V should be very close to the time point guess G. Any difference suggests that the time point guess G is not completely accurate and can be corrected assuming that the signal moves slowly enough. The first correction for each of the left and right PWMs is as follows.
    [52] (6)
    [53] (7)
    [54] In both cases, the corrected natural sample point output is determined by simply summing the interpolated signal value and the correction signal value.
    [55] (8)
    [56] The correction term improves accuracy. Circulation can be introduced to further improve accuracy. Typically, two iterations significantly improve the accuracy. Cycling can be implemented by using the corrected natural sample point output as a new time point guess as provided by the following equations.
    [57] (9)
    [58] 10
    [59] (11)
    [60] The steps of Equations 9-11 can be repeated for improved accuracy. The amount of circulation required to achieve the desired accuracy depends on the oversampling ratio. If the signal travels fast and changes significantly from sample to sample in response to a low oversampling ratio, the need for cycling increases. This is accompanied by additional computational and memory requirements. The complexity of each of the time point estimation step, the interpolation step for calculating the signal value, and the correction value of the signal value can be changed according to the required accuracy. Depending on the accuracy requirements as well as memory and computational constraints, an optimal algorithm can be designed. As an example, in one embodiment of a digital audio amplifier system where the input signal has an input signal limited to 20 kHz bandwidth and 375 kHz PWM switching frequency, the following left equations can be used to achieve extremely good results.
    [61] (12)
    [62] (13)
    [63] (14)
    [64] The corresponding right equations are as follows.
    [65] (15)
    [66] (16)
    [67] (17)
    [68] Note that in this example, the initial time point guess (G) 50 is selected to be the input adjusted PCM signal (U) 28, 128. Since the adjusted PCM signals (U) 28, 128 are already available, there is no computational or memory storage associated with the guess. There are eleven multiplication or addition calculations associated with the calculation of the interpolated signal value (V) 52. There are four memory storage locations needed for this step. The calculation of the corrected natural sample point output requires two additional add or multiply operations and uses one memory storage location. Thus, in this example, a total of 13 operations and 5 memory storage locations are required per samples. At a 375 kHz switching frequency with two samples per switching cycle, the total calculation is 975 million operations per second. Low total memory requirements are particularly advantageous to reduce the overall computational overhead.
    [69] Note that the direct conversion from PCM to PWM is a nonlinear operation that produces an unacceptable total harmonic distortion when no converter such as the PCM-PWM converter 16, 116 is used. Note that the conversion process performed by the PCM-PWM converters 16 and 116 produces a very linear output and therefore does not add significant harmonic components to the PWM signals 30 and 130. Also note that the conversion process performed by the PCM-PWM converters 16 and 116 is very resistant to large amounts of shaped wideband noise often associated with pulse density modulated input signals such as SACD.
    [70] The addition of the duty ratio correction circuit 48 of FIG. 3 may result in a more efficient PCM-PWM converter 16, 116. This PCM-PWM converter 16, 116 can be used for both unidirectional and bidirectional PWM signals. Referring to FIG. 6, the circulation that may be performed in one or more of steps 204, 206, and 207 results in a more accurate PWM signal 30 in which the PCM-PWM converter 16, 116 has less harmonic distortion and approaches theoretical accuracy limits. , 130).
    [71] In one embodiment, the present invention is an all-digital architecture for taking a new SACD audio format and converting it into a digital PWM signal for driving a highly efficient digital switching amplifier. Note that this structure fully accommodates the processing of volume control, graphic equalization and other predetermined digital signal processing functions in the digital domain. Thus, the structure described herein maintains a complete digital path from the PDM input signal to the amplified digital PWM output signal. However, while the present invention has been described in terms of audio signal processing, it is noted that the present invention is applicable to any type of digital signal processing application in which a pulse density modulated data stream or a pulse code modulated data stream is converted to a pulse width modulated signal. It is important to do. Audio signal processing is just one of these applications.
    [72] The method described in FIG. 6 as well as the PCM-PWM converters 16 and 116 shown in FIG. 3 may be used for a wide range of frequencies including radio frequencies. For example, the disclosed circuits and methods may be used as part of a radio frequency amplifier.
    [73] 7 is a block diagram illustrating a general purpose computer 220 used to implement one embodiment of the present invention. General purpose computer 220 includes a computer processor 222 and a memory 224 connected by a bus 226. Memory 224 is a relatively fast machine readable medium and includes volatile memories such as DRAM and SDRAM, and nonvolatile memories such as ROM, FLASH, EPROM, EEPROM, and bubble memory. Secondary storage 230, external storage 232, output devices such as monitor 234, input devices such as keyboard 236 (with mouse), printers 238, and communication link ( One or more other computers 240 connected by 238 are also connected to the bus. Secondary storage device 230 includes machine readable media such as hard disk drives, magnetic drums, and bubble memory. External storage 232 includes floppy disks, removable hard drives, magnetic tape, CD-ROM, and even other computers possibly connected via a communications line. The distinction between secondary storage device 230 and external storage device 232 shown herein is primarily for convenience of description of the invention. As such, it should be understood that there is substantial functional overlap between these elements. Computer software 233 including user programs may be stored in computer software storage media such as memory 224, secondary storage 230, and external storage 232. The secondary storage device 230 and the nonvolatile memory are stored in the secondary storage device 230 before being loaded for direct execution into the volatile memory executed directly from the nonvolatile memory or loaded into the volatile memory for execution.
    [74] Since the apparatus embodying the present invention is composed mostly of electronic components and circuits known to those skilled in the art, the circuit details are as described above for the understanding and recognition of the basic concepts of the present invention and the present invention. It is not described in any large extent deemed necessary in order not to obscure or confuse from the teachings of.
    [75] In the foregoing description, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art will appreciate that various changes and modifications can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
    [76] Advantages, other advantages, and solutions to problems have been described above with reference to specific embodiments. However, advantages, advantages, solutions to problems, and any element (s) that would cause any benefit, advantage, or solution to occur and become more assertive may be a necessary, required part of any or all claims. It should not be considered as an essential feature or element.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] A method for generating a pulse width modulated signal, comprising:
    Receiving a modulated input signal (24) in digital format, wherein the modulated input signal is in the form of pulse density modulation (PDM); And
    Converting (16) the modulated input signal into a pulse width modulation (PWM) form 30 to provide a pulse width modulated signal 30, the conversion step being performed in a completely digital format, Pulse width modulated signal generation method.
    [2" claim-type="Currently amended] The method of claim 1,
    The conversion step,
    And further decimating the modulated input signal 24 to reduce the sampling rate of the modulated input signal and to increase the resolution of the modulated input signal. How to generate a width modulated signal.
    [3" claim-type="Currently amended] The method of claim 1,
    The conversion step,
    Adjusting (14) the modulated input signal by modifying at least one of an amplitude and a frequency response of the modulated input signal.
    [4" claim-type="Currently amended] The method of claim 1,
    The converting step is performed for each of a plurality of predetermined samples,
    Predicting (203) a natural sample time point for sampling the modulated input signal;
    Interpolating (204) the modulated input signal at the predicted natural sample time point to provide an interpolated signal value;
    Providing a correction value to correct an error associated with the predicted natural sample time point (206), wherein the correction value uses the interpolated signal value, the predicted natural sample time point, and the estimated signal slope value. Providing the correction value (206); And
    Combining (207) the correction value and the interpolation signal value to provide a corrected natural sample point output.
    [5" claim-type="Currently amended] In the apparatus 10 for generating a pulse width modulated signal:
    An input terminal for receiving a modulated input signal (24) in digital format, the modulated input signal being in the form of a pulse density modulation (PDM); And
    A converter 20 connected to the input terminal, the converter converts the modulated input signal into a pulse width modulation form to provide a pulse width modulation signal 30, the conversion being performed in a completely digital format And a transducer (20).
    [6" claim-type="Currently amended] The method of claim 5, wherein
    The converter 20,
    And a decimation filter 12 coupled to the input terminal to decimate the modulated input signal to reduce the sampling rate of the modulated input signal and to increase the resolution of the modulated input signal. Signal generator.
    [7" claim-type="Currently amended] The method of claim 5, wherein
    The converter,
    And a digital signal conditioning circuit (14) for adjusting the modulated input signal before converting the modulated input signal into a pulse width modulation form.
    [8" claim-type="Currently amended] The method of claim 7, wherein
    And a filter 18 coupled to the digital signal conditioning circuit to filter the pulse width modulated signal to reject the predetermined frequency components such that the pulse width modulated signal is suitable for driving a load. Pulse width modulated signal generator.
    [9" claim-type="Currently amended] A method for generating a pulse width modulated signal, comprising:
    Receiving a modulated input signal, wherein the modulated signal is one of a pulse code modulation (PCM) form (124) or a pulse density modulation (PDM) form (24);
    Converting the modulated input signal into a pulse width modulation form to provide the pulse width modulation signal 30, 130, the conversion step being executed in a completely digital format,
    The transforming step is performed for each of a plurality of predetermined samples,
    Predicting (203) natural sample time points to sample the modulated input signal;
    Interpolating (204) the modulated input signal at the natural sample time point to provide an interpolated signal value;
    Providing a correction value 206 to correct an error associated with the predicted natural sample time point, wherein the correction value uses the interpolated signal value, the predicted natural sample time point, and an estimated signal slope value. Providing the correction value (206); And
    Combining the correction value (207) and the interpolated signal value to provide a corrected natural sample point output.
    [10" claim-type="Currently amended] In the apparatus (10, 110) for generating a pulse width modulated signal:
    An input terminal for receiving a modulated input signal, the modulated signal being one of a pulse code modulation (PCM) form (124) or a pulse density modulation (PDM) form (24);
    A converter (16, 116) for converting the modulated input signal into a pulse width modulation form to provide the pulse width modulation signal, wherein the conversion is performed in a completely digital format,
    The converter,
    A duty ratio predictor (44) for predicting natural sample time points for sampling the modulated input signal;
    A signal value interpolator (46) coupled to said duty ratio predictor, said signal value interpolator (46) interpolating said modulated input signal at said natural sample time point to provide an interpolated signal value; And
    A correction circuit 48 coupled to the signal value interpolator, the correction circuit providing a correction value to correct an error associated with the predicted natural sample time point, the correction value being the interpolated signal value, the predicted the Provided using natural sample time points and estimated signal slope values, the correction circuit includes the correction circuit 46 that combines the correction values and the interpolation signal values to provide a corrected natural sample point output. A pulse width modulated signal generator.
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    同族专利:
    公开号 | 公开日
    HK1076665A1|2009-12-24|
    JP2005515684A|2005-05-26|
    TWI284459B|2007-07-21|
    CN100483949C|2009-04-29|
    TW200301996A|2003-07-16|
    WO2003061136A1|2003-07-24|
    KR100979075B1|2010-08-31|
    JP4221302B2|2009-02-12|
    AU2002357212A1|2003-07-30|
    EP1466412A1|2004-10-13|
    US6606044B2|2003-08-12|
    CN1615588A|2005-05-11|
    US20030122692A1|2003-07-03|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-01-02|Priority to US10/034,909
    2002-01-02|Priority to US10/034,909
    2002-12-13|Application filed by 모토로라 인코포레이티드
    2002-12-13|Priority to PCT/US2002/039957
    2004-08-11|Publication of KR20040071289A
    2010-08-31|Application granted
    2010-08-31|Publication of KR100979075B1
    优先权:
    申请号 | 申请日 | 专利标题
    US10/034,909|US6606044B2|2002-01-02|2002-01-02|Method and apparatus for generating a pulse width modulated signal|
    US10/034,909|2002-01-02|
    PCT/US2002/039957|WO2003061136A1|2002-01-02|2002-12-13|Method and apparatus for generating a pulse width modulated signal|
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